1. Field of the Invention
The subject matter disclosed herein is concerned with semiconductor memory devices. In particular, the subject matter disclosed herein relates to memory devices that use variable resistance memory devices, and methods of reading data using such memory devices.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application 2005-115629 filed on Nov. 30, 2005, and Korean Patent Application 2005-127038 filed on Dec. 21, 2005, the entire contents of which are hereby incorporated by reference.
2. Description of Related Art
Semiconductor memories are devices capable of selectively storing and recalling data. Semiconductor memory devices are roughly classified into random access memories (RAMs) and read-only memories (ROMs). RAMs are a class of memory that includes dynamic RAMs (DRAMs) and static RAMs (SRAMs). ROMs are a class of memories that include programmable ROMs (PROMs), erasable PROMs (EPROMs), electrically EPROMs, and flash memory devices.
A particular form of programmable ROM that has been growing in popularity is known as “phase-changeable” RAMs (or “PRAMs), which are memory devices that use chalcogenide alloys to store data. One reason for the popularity of PRAMs is that they can be fabricated by simple manufacturing processes relative to other nonvolatile devices, which gives PRAMs an advantage in providing large-capacity storage devices at low cost.
FIG. 1 is an equivalent circuit diagram showing a unit cell of a phase-changeable memory device. Referring to FIG. 1, the unit cell 10 includes a memory element 11 and a selection element 12. The memory element 11 is connected between a bitline BL and the selection element 12. The selection element 12 is connected between the memory element 11 and a ground.
The memory element 11 contains a phage-changeable material, such as Ge—Sb—Te (GST), that can vary in resistance based on its physical state. The physical state of a phase-changeable material can take either a generally crystalline or generally amorphous state, and for the present example the state of the phase-changeable material (GST) (and thus its resistance) can be controlled based on a current supplied through the bitline BL.
The selection element 12 of the unit cell 10 is an NMOS transistor NT. Note that the gate of the NMOS transistor NT is coupled to a wordline WL. When a predetermined voltage is applied to the wordline WL, the NMOS transistor NT is turned on to supply a current to the memory element 11 through the bitline BL. While in FIG. 1 the memory element 11 is connected between the bitline BL and the selection element 12, the selection element 12 may be connected between the bitline BL and the memory element 11.
FIG. 2 is an equivalent circuit diagram showing another unit cell 20 of a phase-changeable memory device. Referring to FIG. 2, the unit cell 20 includes a memory element 21 and a selection element 22 with the memory element 21 connected between a bitline BL and the selection element 22. The present memory element 21 is the same as the memory element 11 shown in FIG. 1. The present selection element 22 is composed of a diode D.
In operation, when a voltage difference between the anode and cathode of the selection element 22 (diode D) becomes higher than the diode's threshold, the selection element 22 is turned on to supply a current to the memory element 21 through the bitline BL. Accordingly, the resistance of the memory element 21 can be measured during read operations, and heat can be applied during write operations.
FIG. 3 is a graph showing the operational characteristics of the GST phase-changeable material used in the unit cells 10 and 20 shown FIGS. 1 and 2. Referring to FIG. 3, the reference numeral 1 denotes a characteristic curve representing a change of the GST phase-changeable material to an amorphous state, while the reference numeral 2 denotes a characteristic curve representing a change of the GST phase-changeable material to a crystalline state.
Referring to reference curve 1, the GST phase-changeable material can turn to its amorphous state by heating the GST phase-changeable material to a temperature higher than its melting point Tm using a controlled current for a time T1 and then quenching the temperature. The amorphous state, also known as the ‘reset state’, is used to store a data ‘1’ within the GST phase-changeable material.
Referring next to reference curve 2, the GST phase-changeable material can turn to its crystalline state by heating it up to a temperature higher than its crystallization temperature Tc and lower than the melting temperature Tm using a controlled current for a time T2 (typically longer than T1) and then cooling GST phase-changeable material relatively slowly. The crystalline state is called the ‘set state’ and is used for storing a data ‘0’. Note that the resistance of the GST phase-changeable material is higher in the amorphous state than in the crystalline state.
A normal phase-changeable memory device having a plurality of memory cells can accept an external power source voltage VCC to precharge its bitlines BL and/or supply read current to the bitline BL. For read operations, a phage-changeable memory device generally employs a precharging circuit, a bias circuit, and a sense amplifier. The precharging circuit preliminarily charges the bitline BL up to the power source voltage VCC. The bias circuit supplies the read current to the bitline BL from the power source voltage VCC. The sense amplifier compares a voltage of a sensing node with a reference voltage, and reads data from the memory cell.
However, during a read operation a “sensing margin” of the sense amplifier can inadvertently be reduced or the power source voltage VCC can decrease below a predetermined voltage level (e.g., 1.5V). A sensing margin is the voltage difference between the reset and set states at the sensing node in a memory cell. For embodiments where the selection element uses an NMOS transistor (e.g., memory cell 10 of FIG. 1) and the power source voltage VCC is 1.5V, the sensing-node is maintained at about 1.5V if the memory cell is configured in the reset state. However, the sensing node will be reduced from the power source voltage VCC to the ground level if the memory cell is configured in the set state.
On the other hand, in the case where a selection element of a memory cell is formed from a diode (e.g., memory cell 20 of FIG. 2), the sensing node will be maintain at about 1.5V when the memory cell 20 is maintained in the reset state, but the sensing node will be reduced to the threshold voltage of the diode when if the memory cell is configured to the set state. For this reason, the sensing margin of a phase-changeable memory device employing a diode D as a selection element is reduced by the threshold voltage of the diode D. The sensing margin is further reduced when the threshold voltage of the diode D rises due to factors arising from the diode's fabrication process.
Therefore, is can be advantageous to improve the sensing margin of phase-changeable memories that use diodes as selection elements during read operations.